tm
TE
CH
Preliminary T15V4M08A
SRAM
FEATURES
•
Low-power consumption
- Active: 40mA at 55ns
- Stand-by: 10uA (CMOS input/output)
•
55/70/100 ns access time
•
Equal access and cycle time
•
Single +2.7V to 3.6V Power Supply
•
TTL compatible , Tri-state output
•
Common I/O capability
•
Automatic power-down when deselected
•
Available in 32-pin TSOP-I(8x13.4mm) and
48-pin CSP packages
512K X 8 LOW POWER
CMOS STATIC RAM
GENERAL DESCRIPTION
The T15V4M08A is a very Low Power
CMOS Static RAM organized as 524,288 words by
8 bits . This device is fabricated by high
performance CMOS technology. It can be
operated under wide power supply voltage range
from +2.7V to +3.6V.
The T15V4M08A inputs and three-state
outputs are TTL compatible and allow for direct
interfacing with common system bus structures.
Data retention is guaranteed at a power supply
voltage as low as 1.5V.
PART NUMBER EXAMPLES
PART NO.
T15V4M08A-55C
T15V4M08A-70P
PACKAGE CODE
P= TSOP-I(8x13.4)
C = CSP
Vcc
Vss
A0
.
.
.
A18
DECODER
CORE
ARRAY
WE
OE
CE
CONTROL
CIRCUIT
DATA I/O
I/O1
.
.
.
I/O8
BLOCK DIAGRAM
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: MAR. 2001
Revision:0.A
tm
A11
A9
A8
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
TE
CH
Preliminary T15V4M08A
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
TSOP-I
(8x13.4mm)
1
A
B
C
D
E
F
G
H
A0
2
A1
3
N C
4
A3
5
A6
6
A8
I/O5
A2
W E
A4
A7
I/O1
I/O6
N C
A5
I/O2
VSS
48-CSP
TOP VIEW
VCC
VCC
VSS
I/O7
A18
A17
I/O3
I/O8
O E
CE
A16
A15
I/O4
A9
A10
A11
A12
A13
A14
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A18 Address inputs
I/O1~I/O8 Data inputs/outputs
CE
WE
SYMBOL DESCRIPTIONS
OE
Output enable input
Power supply
Ground
No connection
VCC
V
SS
NC
Chip enable
Write enable input
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: MAR. 2001
Revision:0.A
tm
TE
CH
Preliminary T15V4M08A
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on Any Pin Relative to V
SS
Power Dissipation
Storage Temperature
Temperature Under Bias
SYM
V
R
P
D
T
STG
I
BIAS
MIN.
-0.2
-
-55
-40
MAX.
+3.6 V
0.7
+150
+85
UNIT
V
W
°C
°
C
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
WE
OE
DATA
MODE
CE
Standby
H
X
X
High-Z
L
H
L
Data Out
Active, Read
L
H
H
High-Z
Active, Output Disable
L
L
X
Data In
Acitve, Write
*Note: X = Don’t Care (Must be low or high state), L = Low, H = High
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: MAR. 2001
Revision:0.A
tm
TE
CH
Preliminary T15V4M08A
OPERATING CHARACTERISTICS
(Vcc = 2.7 to 3. 6V, Vss = 0V, Ta = -40
°
C to 85
°
C)
PARAMETER
Input Leakage
Current
Output Leakage
Current
SYM.
TEST CONDITIONS
-55
Min
Max
-70
Min
Max
-100
Min
Max
UNIT
uA
I
LI
Vcc = Max,
V
IN
= Vss to Vcc
CE
= V
IH
or
OE
= V
IH
I
LO
or
WE
= V
IL
V
OUT
= Vss to Vcc
CE
= V
IL
,
WE
=V
IH,
OE
= V
IH
,
-
1
-
1
-
1
-
1
-
1
-
1
uA
Operating Power
Supply Current
I
CC
I
CC1
Average Operating
Current
I
CC2
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
Cycle time=1us,
100% duty, I
OUT
=0mA,
CE
≤
0.2V,V
IN
≤
0.2V
or V
IN
≥
Vcc-0.2V
Cycle time=min,
100% duty, I
OUT
=0mA,
CE
= V
IL
,
V
IN
= V
IH
or V
IL
CE
=
V
IH
-
2
-
2
-
2
mA
-
3
-
3
-
3
mA
-
40
-
35
-
25
mA
Standby Power
Supply Current
(TTL Level)
Standby Power
Supply Current
(CMOS Level)
Output Low Voltage
Output High Voltage
I
S B
V
IN
= V
IH
or V
IL
CE
≥
Vcc-0.2V,
-
0.3
-
0.3
-
0.3
mA
I
S B1
V
OL
V
OH
V
IN
≤
0.2V or
V
IN
≥
Vcc-0.2V
-
-
2.2
10
0.4
-
-
-
2.2
10
0.4
-
-
-
2.2
10
0.4
-
uA
V
V
I
OL
= 2.1mA
I
OH
= -1.0 mA
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: MAR. 2001
Revision:0.A
tm
TE
CH
Preliminary T15V4M08A
RECOMMENDED OPERATING CONDITIONS
(Ta = -40
°
C to 85
°
C)
PARAMETER
Supply Voltage
Input Voltage
SYM
Vcc
Vss
MIN
2.7
0.0
0.7Vcc
-0.2
TYP
3.0
0.0
-
-
MAX
3.6
0.0
Vcc+0.3
0.6
UNIT
V
V
V
V
V
IH
V
IL
CAPACITANCE
(f = 1 MHz, Ta = 25
°
C,)
PARAMETER
Input Capacitance
Input/ Output Capacitance
SYMBOL
CONDITION
V
IN
= 0V
V
IN
=
V
OUT
= 0V
MAX.
8
10
UNIT
pF
pF
C
IN
C
I /O
Note:
This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
CONDITIONS
0.6V to 0.7Vcc
3.0 ns
1.4V
C
L
=30pF+1TTL Load(55ns/70ns)
C
L
=100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
TTL
DQ
R
L
50 ohm
C
L
*
Z
0
C
L
30 pF
= 50 ohm
Vt =1.4V
Fig.A * Including Scope and Jig Capacitance
Fig.B Output Load Equivalent
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: MAR. 2001
Revision:0.A
